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Uniformity
The critical success factor
Mask Uniformity
Path to wafer uniformity
Wafer Uniformity
Achieving the best process window
GPU Acceleration
Practical full-reticle processing
Curvilinear
Better mask and wafer quality
Pixel Domain
Shape-agnostic computing
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PLDC
MPC for uniformity and linearity
TrueMask
®
ILT
Full-chip, Entirely Manufacturable™ ILT
TrueModel
®
Physical model for masks and wafers
CDP
GPU-accelerated design platform
About D
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S
About D
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S
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2
S Technology Highlights
Technologies
Uniformity
The critical success factor
Mask Uniformity
Path to wafer uniformity
Wafer Uniformity
Achieving the best process window
GPU Acceleration
Practical full-reticle processing
Curvilinear
Better mask and wafer quality
Pixel Domain
Shape-agnostic computing
Products
PLDC
MPC for uniformity and linearity
TrueMask
®
ILT
Full-chip, Entirely Manufacturable™ ILT
TrueModel
®
Physical model for masks and wafers
CDP
GPU-accelerated design platform
About D
2
S
About D
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S
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Page 33
D
2
S Unveils eBeam Solution that Both Reduces Photomask Write Time and Improves Photomask Accuracy at 20‐nm Node and Beyond
Press Release • September 11, 2012
TrueMask
®
MDP is the First and Only Model‐Based Mask Data Preparation Solution to Process Full‐Chip Design Data for Production Applications
English
日本語
eBeam Initiative Roadmap to Focus on Semiconductor Photomask Critical Dimension Uniformity at SPIE Advanced Lithography 2012 Symposium – Proof Points at SPIE demonstrate the ability of eBeam Technologies to Improve 20-nm and 14-nm Wafer Yields
Press Release • February 13, 2012
Proof points at SPIE Advanced Lithography demonstrate the ability of eBeam technologies to improve 20‐nm and 14‐nm wafer yields
English
日本語
D
2
S Expands Management Team with Photomask and Semiconductor Industry Veterans – New Hires from Intel, KLA-Tencor and Synopsys Bring Wealth of Semiconductor Experience as D
2
S Enters Next Stage of Growth
Press Release • February 13, 2012
New Hires from Intel, KLA‐Tencor and Synopsys Bring Wealth of Semiconductor Experience as D
2
S Enters Next Stage of Growth
English
日本語
DFeB Technology Leader D
2
S Appoints New President of Japanese Subsidiary
Press Release • October 1, 2011
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D
2
S Unveils Industry's First Mask-Wafer Double Simulation Platform
Press Release • September 20, 2011
TrueMask
®
DS enables interactive optimization of mask write‐times and wafer quality
English
日本語
D
2
S Taps Industry Semiconductor EDA Veteran to Serve as Vice President of Engineering
Press Release • March 29, 2011
D
2
S Fills Critical Role as Momentum Builds to Support Cost‐Effective 20‐nm Optical Lithography
English
日本語
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