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D2S has rethought the semiconductor manufacturing data flow from the ground up using GPU-accelerated, pixel-based computing. D2S technologies take the flow from design to mask and through wafer manufacturability checking. All along the way, wafer and mask designs can be conventional Manhattan designs or Entirely Manufacturable™, and therefore entirely curvilinear, designs or fall anywhere in between and still reap the same benefits in terms of accuracy and computing speed. This is because D2S GPU-accelerated, pixel-based computing is agnostic to input shape.

D2S software applications are based on NVIDIA CUDA, a parallel-computing platform and programming model for graphical processing units (GPUs). The D2S Computational Design Platform (CDP) is purpose-built to form a pixel-based computing appliance with the D2S software solutions. D2S envisions an Entirely Manufacturable wafer-design-to-mask-writer data path for IC manufacturing where the D2S CDP is the computational engine shared by GPU-accelerated pixel-based applications. Together they form a co-optimized GPU-accelerated appliance for physics-based computing for IC manufacturing to improve uniformity and linearity for wafers and masks.

The newest-generation D2S CDP with GPU acceleration offers 18,000 TFLOPS (FP32) of computing power in a two-rack CDP – enabling simulation-based, accurate manipulation and analysis of Manhattan or curvilinear shapes. 18,000,000,000,000,000 floating point operations per second is the rate of computing on a CDP. D2S CDPs enable Entirely Manufacturable and therefore entirely curvilinear shapes using pixel-based computing, without the need for additional core computing. Entirely curvilinear processing is not practical with edge-based processing that CPU-based applications must use, and therefore applications that are ported from CPUs to GPUs use.

From creating and processing complex mask shapes to helping to write the masks and analyzing mask SEM data to utilizing deep learning models for accuracy and runtime improvements, D2S GPU-accelerated solutions help customers to achieve manufacturing success on their leading-edge mask and chip designs.

Features

  • Scalable from one- to eight-rack solutions for full-reticle processing
  • Purpose-built to optimize performance for simulation-based semiconductor design and manufacturing applications
  • Reliable for 24×7 operations, including cleanroom production environments
  • Features NVIDIA L40S GPUs
  • Comprises 18,000 TFLOPS (FP32) of computing power in a two-rack CDP

Benefits

  • Enables Entirely Manufacturable and therefore entirely curvilinear data processing
  • Enables front-to-back pixel-based computing solution from mask design, wafer manufacturability check, mask manufacturability check, and PLDC
  • Offers software-based differentiation to embed in semiconductor manufacturing equipment
  • Provides >100X in core computing of scientific, image, and neural-network computing
  • Scales naturally over time with standard parts unlike custom ASICs and FPGAs

D2S CDPs Deployed Worldwide in a Variety of Manufacturing Settings

Reliability is always a key concern for any computing platform. The cleanroom-proven D2S CDP is designed to keep mission-critical production lines up and running and minimizes costly downtime.

Semiconductor manufacturing leaders have deployed the D2S CDP in more than 65 installations worldwide.