Inverse lithography technology (ILT) creates ideal lithography results through a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results. The semiconductor industry has long recognized the value of curvilinear ILT for improving process windows for advanced nodes. However, until now, weeks-long runtimes have held curvilinear ILT back from use as a full-chip solution.
D2S TrueMask® ILT combines a unique stitchless approach with GPU acceleration to make full-chip, curvilinear ILT in a day a practical reality.
For more than a decade, it has been established that unconstrained curvilinear ILT results in the best process windows. However, two major obstacles have kept curvilinear ILT from being widely applied. One of these barriers – the ability to write curvilinear mask patterns – has been removed recently by the introduction of multi-beam mask writers, which can write any shape without time penalty. The other major barrier – conventional ILT runtimes – has been seemingly insurmountable. This barrier has now been overcome by TrueMask® ILT.
Micron and D2S presented a joint paper at SPIE Photomask Technology 2019 (Best Paper, Oral Presentation — 2nd Place) that confirmed that TrueMask® ILT produces a much larger process window than OPC, and demonstrated the high quality of TrueMask® ILT mask results in terms of continuity and symmetry.
Linyong Pang, Ezequiel Vidal Russell, Bill Baggenstoss, Michael Lee, Jennefir Digaum, Ming-Chuan Yang, P. Jeffrey Ungar, Ali Bouaricha; Kechang Wang, Bo Su, Ryan Pearman, Aki Fujimura, “Study of mask and wafer co-design that utilizes a new extreme SIMD approach to computing in memory manufacturing: full-chip curvilinear ILT in a day,” Proc. SPIE 11148, Photomask Technology 2019 (October 3, 2019). DOI: https://doi.org/10.1117/12.2534629
In August, 2021, SPIE published Leo Pang’s review of 30 years of ILT development, “Inverse lithography technology: 30 years from concept to practical, full-chip reality,” SPIE 2021, DOI: 10.1117/1.JMM.20.3.030901
By embracing a “from the ground up” approach, D2S was able to conceive a holistic, purpose-built system of GPU-accelerated hardware and software that is designed and implemented specifically for GPU-acceleration and for full-chip, curvilinear ILT computation. Every aspect of the physics and chemistry of wafer lithography and processing, including litho simulations, mask and wafer models has been optimized synergistically throughout the system in order to reap the largest potential run-time benefits without compromising computational accuracy.
Most significantly, TrueMask® ILT embodies a unique, stitchless approach. Although the D2S computational design platform (CDP) employed by TrueMask® ILT includes many GPU/CPU pairs, it emulates a single, giant GPU/CPU pair that can optimize the entire chip as a whole, making full-chip, curvilinear ILT in a day a practical reality.
Partitioning and stitching – the conventional approach to runtime improvement – hasn’t worked for full-chip ILT, as they result in lengthy and recursive computations to correct the inevitable errors on partition borders. The stitchless approach of TrueMask® ILT iterates on the entire chip at once, eliminating stitching errors.
“In our joint study with D2S, we examined the benefits of a mask and wafer co-design, which leverages and maximizes GPU acceleration to implement full-chip curvilinear ILT for advanced semiconductor memory manufacturing. The results of this joint study show that curvilinear ILT provides larger process windows compared to conventional ILT or complex OPC.”
